The present invention generally relates to processor control, and more specifically, to control of processor clock rate.
Many systems which utilize a microprocessor have two competing requirements: power consumption and processing power. The power requirements of a CMOS microprocessor are based on the frequency at which the digital circuits are switching. The current requirement is an approximately
ITotal=(ngxc3x97Iq)+(ƒxc3x97nintxc3x97Iint)+(ƒxc3x97nextxc3x97Iext) 
linear function, summarized by
where Iq is the quiescent current of each gate, ng is the total number of gates, ƒ is the frequency, nint is the average number of internal gates which are switching, Iint is the current required to switch an internal gate, next is the average number of external pads which are switching and Iext is the current required to switch an external pad.
Typically, Iq tends to be very small in relation to Iint and Iext. Therefore, by adjusting the frequency of switching f, the amount of current required by the circuit can be controlled. Since power is equal to current multiplied by voltage, and voltage is a fixed value, the power will be modified accordingly.
A system designer attempting to reduce the processor""s power requirement by using a lower processor clock rate typically runs into a problem: a processor with a lower clock rate does not have enough MIPs (million instructions per second) to meet the system""s processing requirements. Because each instruction takes a specific number of clock cycles to execute, reducing the clock rate increases the time it takes to execute the same number of instructions. Below a minimum clock rate threshold, the system does not have enough time to carry out its required tasks, for example, updating graphics on a screen or buffering incoming data. A second problem with using a reduced clock rate is the increased time required for the processor to handle an interrupt from an I/O device. On some devices, interrupts must be handled quickly, so that reducing the clock rate fails this requirement.
One approach used in prior systems to solve this problem was to use a clock rate high enough to meet system processing requirements, while reducing power consumption by occasionally putting the processor into a low-power state, in which the processor does not execute instructions. One version of this approach relies on a hardware timer that, after some period of inactivity, expires and puts the processor into a low-power state. However, power consumption is still not optimal because the processor runs at its maximum clock rate whenever it executes instructions. Another variation on this approach puts the processor into a low-power state whenever the operating system is in an idle state (no actively running tasks). This approach is also non-optimal because the processor runs at its maximum clock rate whenever it is actively running a task.
Thus, there is a need for a microprocessor-based system that addresses, among others, the above-noted problems of power consumption and processing requirements.
To achieve various objects and advantages, the preferred embodiment of the present invention is directed to an apparatus and method to control processor clock rates. A microprocessor-based system is partitioned into threads. The preferred embodiment of the present invention takes advantage of differences in thread processing requirements by running some threads at a high processor clock rate and other threads at a lower processor clock rate.
Other objects, features, and advantages of the present invention will become apparent to one skilled in the art upon examination of the following drawings and detailed description. It is intended that all such additional objects, features, and advantages be included herein within the scope of the present invention, as defined by the claims.